Generally, a phase locked loop (PLL) circuit includes a phase comparator, a charge pump, a loop filter, and a voltage controlled oscillator (VCO), which configure a loop (see Patent Document 1). The PLL circuit is used as a frequency synthesizer outputting an oscillation signal having a frequency obtained by multiplying a frequency of an input oscillation signal by a constant. In addition, the PLL circuit can recover a clock embedded in an input digital signal in a clock data recovery (CDR) apparatus.
The PLL circuit operates as follows. If a control voltage value is input to the voltage controlled oscillator, an oscillation signal having a frequency corresponding to a control voltage value thereof is output from the voltage controlled oscillator. The oscillation signal output from the voltage controlled oscillator or a signal obtained by dividing the oscillation signal is input to the phase comparator as a feedback oscillation signal. In addition to this feedback oscillation signal, another input signal (the oscillation signal or a digital signal) is also input to the phase comparator. In the phase comparator, a phase difference between the input signal and the feedback oscillation signal is detected, and a phase difference signal representing the detected phase difference is output to the charge pump.
The charge pump receiving the phase difference signal outputs a charging and discharging current according to the phase difference represented by the phase difference signal. The charging and discharging current is input to the loop filter. The loop filter includes a resistor and a first capacitance element connected in series with each other, and also includes a second capacitance element provided in parallel to the resistor and the first capacitance element. The loop filter outputs a control voltage value increased or decreased according to the amount of charging and discharging to the voltage controlled oscillator. The control voltage value output from the loop filter is input to the voltage controlled oscillator, and the oscillation signal having a frequency corresponding to the control voltage value is output from the voltage controlled oscillator.
In the PLL circuit including the loop, the control voltage value output from the loop filter and input to the voltage controlled oscillator converges to a certain value such that the phase difference detected by the phase comparator is reduced. The oscillation signal having a frequency obtained by multiplying the frequency of the input oscillation signal by a constant is output from the voltage controlled oscillator, or the clock embedded in the input digital signal is recovered and output.
Patent Document 1: Japanese Patent No. 4089030